// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:07 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  gen_clk_mux.v
//
//  Generic balanced mux for synthesis use
//
//  Original Author: Ross Segelken
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pma/dig/rtl/gen_clk_mux.v $
//    $DateTime: 2013/09/13 14:31:34 $
//    $Revision: #2 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_ani_techcell_lib.v"

module dwc_e12mp_phy_x4_ns_gen_clk_mux (
output wire out,
input  wire sel,
input  wire d0,
input  wire d1
);

// %%SYNTH:
//   set_dont_touch [get_cells $inst/*hand_mux]
//
`ifdef ANI_SYNTH_MODE
   dwc_e12mp_phy_x4_ns_ani_clk_mux hand_mux(.Y(out),
                        .S0(sel),
                        .A(d0),
                        .B(d1));
`else
    assign out = sel ? d1 : d0;
`endif

endmodule
